This invention relates to the field of monolithic circuits and, in particular, to phase locked loop systems.
The phase-locked loop (PLL) concept has been used in communications systems for years. Until recently, however, phase-locked systems have been too complex and costly for use in most consumer and industrial systems, where performance requirements are less stringent and cost requirements more stringent. However, PLLs are increasingly being used in many applications such as stereo demodulators, tone detectors, frequency synthesizers, networking systems, and others.
A PLL is used to lock the frequency of an output signal to that of an input signal (e.g., a reference signal), where the frequency of the input signal varies over time. A PLL contains a phase detector, a loop filter, an amplifier, and a voltage-controlled oscillator (VCO). The VCO is an oscillator that generates a signal (e.g., a clock signal) whose frequency is proportional to an externally applied voltage. When the loop is locked on the reference signal, the VCO frequency is configured to be exactly equal to that of the input signal.
The phase detector is an asynchronous circuit that may be used to lock, or synchronize, the clock signal generated by the VCO to the reference clock signal. The phase detector compares the rising clock edges of the VCO clock signal and the reference clock signal and sends out a digital pulse to an analog loop filter. The loop filter converts the pulse into a voltage that may be used to control the voltage on the VCO in such a way as to bring the VCO frequency back to the same value as the input reference signal. Once the VCO is locked to the reference clock signal, the pulse from the phase detector is set at a fixed width.
FIG. 1A illustrates one prior art phase detector. Inside the phase detector are two flip-flops that are driven by either the VCO clock signal or the reference clock signal. A reset signal may be generated by the two flip-flops when the rising edge of both clock signals is detected. The reset signal is used to reset the two flip-flops.
One problem with such a phase detector circuit when implemented on a programmable logic device (PLD), such as field programmable gate array (FPGA), is that manufacturing process variations in the components of the circuit may cause differences in the propagation delay of the reset signal when routed to various blocks of the circuit. As a result, only one of the two flip-flops may be reset with the other flip-flop not being reset, thereby causing the reset signal to be disabled. When the next clock rising edge goes into the non-reset flip-flop, the clock rising edge cannot be detected.
For example, when the phase detector circuit receives a rising clock edge from the reference clock, the UP output signal goes to xe2x80x9c0.xe2x80x9d Then, the circuit is waiting for the rising edge from the VCO clock. Once the rising edge of the VCO clock signal arrives, the DOWN output signal goes to xe2x80x9c0xe2x80x9d and causes the RESET signal to go to xe2x80x9c1.xe2x80x9d The RESET signal resets both flip-flops back to xe2x80x9c1,xe2x80x9d after which the circuit waits for the rising edges from the next clock cycle. When such a circuit is implemented in a large circuit design, there may be no way to control the routing of each segment of the RESET signal.
FIG. 1B is a timing diagram illustrating the timing relationships of signals in the phase detector of FIG. 1A having different RESET signal length segments. If segment xe2x80x9caxe2x80x9d of the RESET signal is routed much more shorter than segment xe2x80x9cb,xe2x80x9d once RESET is enabled, the flip-flop for the reference clock is reset back to xe2x80x9c1.xe2x80x9d This may cause the RESET to disable before the flip-flop for the VCO clock receives the RESET enable. As a possible result, the DOWN output signal may always be at xe2x80x9c0xe2x80x9d and, thus, the circuit cannot perform its intended function. Such routing problems may be especially prevalent when die-shrinking existing circuit designs.
The present invention pertains to an apparatus for and method of compensating for differences in routing path lengths in a phase detector. In one embodiment, the apparatus may include a first flip-flop having an output and a control input and a second flip-flop having an output and a control input. The apparatus also includes a first logic gate having an output, a first input coupled to the output of the first flip-flop, and a second input coupled to the output of the second flip-flop. The apparatus also includes a latch having a control input coupled to the output of the logic gate and an output coupled to the control inputs of the first and second flip-flops.
In one embodiment, the method may include receiving a first output from a first flip-flop and receiving a second output from a second flip-flop, and generating a first value for a reset signal based on the first and second outputs. The method also includes detecting a state change on the first and second outputs and holding the first value of the reset signal until the state change is detected on both the first and second outputs.
Additional features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.